A) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device having field effect transistors having a fin-type structure and its manufacture method.
A field effect transistor having a fin-type structure is generally called Fin-FET or double-gate Fin-FET and is a three-dimensional field effect transistor having a channel plane vertical to a substrate plane. A semiconductor protrusion of a thin wall (fin) vertical to the plane of a substrate is formed, a gate insulating film and a gate electrode are formed on each of side walls of the fin, and source/drain regions are formed in the fin on both sides of the gate electrode.
B) Description of the Related Art
A field effect transistor having a fin type structure has a channel plane vertical to the substrate surface so that an occupied area of the substrate can be reduced, dielectric separation is facilitated and adaptability to micro structure and high speed operation can be enhanced. A semiconductor on insulator (SOI) substrate has a silicon layer disposed on an insulating film, and a cap layer of an oxide film, a lamination of an oxide film and a nitride film or the like is formed on the silicon layer of the SOI substrate, and the cap layer and silicon layer are patterned to form a fin of silicon. A gate insulating film of silicon oxide, silicon oxynitride or the like is formed on the fin surface, and thereafter a polysilicon layer is deposited and patterned to form an insulated gate electrode. Impurities are doped in the fin region on both sides of the gate electrodes to form source/drain regions. In this manner, a basic FET structure can be formed.
FIG. 7 shows an example of the structure of Fin-FET. Referring to FIG. 7, the silicon layer of an SOI substrate having an SiN/SiO2 cap layer is patterned to form a fin 51 and contact regions 52 and 53 having an increased width on both sides of the fin. A sacrificial oxide film is formed on the fin side walls, and the SiN layer together with the sacrificial oxide film are removed. The cap layer 61 is left on the silicon layer. A gate insulating film 62 is formed through oxidation, nitridation or the like. A polysilicon layer is deposited on the substrate and patterned to form a gate electrode 71. A contact region 72 having an increased width is formed at one end of the gate electrode 71. Impurities are doped by ion implantation or the like to form source/drain regions. After the transistor structure is buried in an interlayer insulating film, contact holes reaching the contact areas are formed through the interlayer insulating film, and conductive plugs 80 such as tungsten plugs are buried in the contact holes. The gate electrode resistance can be lowered by using as the gate electrode a lamination of a polysilicon layer and a silicide layer.
For these technologies, refer to “2002 Symposium on VLSI Technology Digest of Technical Papers” by Fu-Liang Yang et al., p. 104, 2002 or “IEDM Tech. Dig.” by Bin Yu et al., p. 251, 2002.
The channel of Fin-FET is formed in the silicon layer facing the gate electrode via the gate insulating film. The channel length is determined by the width of the gate electrode (polysilicon layer) and the channel width is determined by the height of the fin. Although the length of the fin is determined by a process precision and the like, the narrow lead regions of the source/drain regions increase the resistance of the source/drain regions. There is a proposal that without broadening the opposite end portions of a fin, opposite end portions of the fin are cut and metal layers are buried to form Schottky contacts (e.g., refer to Japanese Patent Laid-open Publication No. 20002-289871).